Semiconductor device with STI and its manufacture

ABSTRACT

A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is based on Japanese Patent Application No.2002-074871, filed on Mar. 18, 2002, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] A) Field of the Invention

[0003] The present invention relates to a semiconductor device and itsmanufacture method, and more particularly to a semiconductor devicehaving shallow trench isolation (STI) and its manufacture method.

[0004] B) Description of the Related Art

[0005] Local oxidation of silicon (LOCOS) is known as one method for theelement isolation of a semiconductor device.

[0006] According to LOCOS technique, a silicon oxide film is formed on asilicon substrate as a buffer layer, thereafter a silicon nitride filmas an oxidation prevention film is formed, the silicon nitride film ispatterned and then the surface of the silicon substrate is thermallyoxidized.

[0007] While the silicon substrate is thermally oxidized, oxidizingspecies such as oxygen and moisture invade the buffer silicon oxidefilm. As a result, the silicon substrate surface under the siliconnitride film is oxidized and silicon oxide regions having a shape calleda bird's beak are formed. These bird's beak regions cannot be usedsubstantially as an element forming region (active region) so that thearea of the active region is reduced.

[0008] If the surface of a silicon substrate is thermally oxidized byusing a silicon nitride film pattern having openings of various sizes,the thickness of a silicon oxide film formed on the silicon substratesurface in an area corresponding to an opening of a smaller size isthinner than that of a silicon oxide film formed in an areacorresponding to an opening of a lager size. This phenomenon is calledthinning.

[0009] The area not used as the active region in the whole area of asemiconductor substrate increases because of bird's beaks and thinningwhich occur more often as semiconductor devices are made finer. Namely,since a ratio of the active region to the whole substrate area issubstantially lowered, high integration of semiconductor devices ishindered.

[0010] Trench isolation (TI) technique is know as the technique offorming active regions by which a trench is formed in the surface layerof a semiconductor substrate and insulating material or polysilicon isfilled in the trench. This method has been used bipolar transistor LSIswhich require a deep isolation region.

[0011] Application of trench isolation technique to MOS transistor LSIsis prevailing because of no bird's beak and thinning. Isolation for aMOS transistor LSI does not require as deep isolation as that of abipolar transistor LSI and can be realized by a relatively shallowtrench of about 0.1 to 1.0 μm. This is called a shallow trench isolation(STI) structure.

[0012] With reference to FIGS. 9A to 9H, an STI process will bedescribed.

[0013] As shown in FIG. 9A, on the surface of a silicon substrate 1, asilicon oxide film 2 having a thickness of, e.g., 10 nm is formed bythermal oxidation. On this silicon oxide film 2, a silicon nitride film3 having a thickness of e.g., 100 to 150 nm is formed by chemical vapordeposition (CVD). The silicon oxide layer 2 functions as a buffer layerfor relaxing a stress between the silicon substrate 1 and siliconnitride film 3. The silicon nitride film 3 is functions also as astopper layer during a later polishing process.

[0014] A resist pattern 4 is formed on the silicon nitride film 3. Anopening defined by the resist pattern 4 defines an area in which theactive region is formed. The region of the silicon substrate under theresist pattern becomes an active region where device elements areformed.

[0015] By using the resist pattern 4 as an etching mask, the siliconnitride film 3 exposed in the opening and the underlying silicon oxidefilm 2 and silicon substrate 1 are etched to a depth of, e.g., about 0.5μm by reactive ion etching (RIE) to form a trench 6. Thereafter, theresist pattern 4 is removed.

[0016] As shown in FIG. 9B, the silicon substrate surface exposed in thetrench 6 is thermally oxidized to form a silicon oxide film 7 having athickness of, e.g., 10 nm.

[0017] As shown in FIG. 9C, burying the trench, a silicon oxide layer 9is deposited over the silicon substrate, for example, by high densityplasma (HDP) CVD. In order to make dense the silicon oxide film 9 as theisolation region, the silicon substrate is annealed, for example, in anitrogen atmosphere at 900 to 1100° C.

[0018] As shown in FIG. 9D, by using the silicon nitride film 3 as astopper, the silicon oxide layer 9 is etched downward by chemicalmechanical polishing (CMP) or reactive ion etching (RIE). The siliconoxide film 9 is left only in the trench defined by the silicon nitridefilm 3. At this stage, annealing may be performed for making siliconoxide dense.

[0019] As shown in FIG. 9E, the silicon nitride film 3 is removed byusing hot phosphoric acid. Next, the buffer silicon oxide film 2 on thesurface of the silicon substrate 1 is removed by using dilutehydrofluoric acid. At this time, the silicon oxide film 9 buried in thetrench is also etched.

[0020] As shown in FIG. 9F, the surface of the silicon substrate 1 isthermally oxidized to form a sacrificial silicon oxide film 22 on thesilicon substrate 1 surface. Impurity ions of a predeterminedconductivity type are implanted into the surface layer of the siliconsubstrate 1 via the sacrificial silicon oxide film, and activated toform wells 10 of the predetermined conductivity type in the siliconsubstrate 1.

[0021] The sacrificial silicon oxide film 22 is thereafter removed byusing dilute hydrofluoric acid. While the sacrificial silicon oxide filmis removed, the silicon oxide layer 9 is also etched by the dilutehydrofluoric acid. By a plurality of hydrofluoric acid processes, thesilicon oxide layer 9 buried in the trench is etched so that a dug divotor indent is formed along the side of the active region.

[0022] As shown in FIG. 9G, the surface of the exposed silicon substrateis thermally oxidized to form a silicon oxide film 11 having a desiredthickness which film is used as the gate insulating film. A polysiliconlayer 12 is deposited over the silicon substrate 1, and patterned toform a gate electrode. Impurity ions of the conductivity type oppositeto that of the wells 10 are implanted and activated to form source/drainregions. If necessary, side wall spacers are formed on the side walls ofthe gate electrode, and impurity ions are again implanted and activatedto form high impurity concentration source/drain regions.

[0023]FIG. 9H shows the characteristics of drain current relative togate voltage of a transistor manufactured as above. The abscissarepresents gate voltage and the ordinate represents drain current. Acurve r shows the characteristic of a normal transistor. A curve h showsthe characteristics of a transistor formed by the above-describedprocesses. As seen from the curve h, the drain current starts flowing ata lower gate voltage. This analysis results in that a parasitictransistor turning on at a low threshold voltage is added.

[0024] If the shoulder S of the isolation region 9 is etched and divotsor recesses are formed as shown in FIG. 9G, the shoulder of the activeregion of the silicon substrate is surrounded by the gate electrode notonly from the upper surface of the active region but also from the sidethereof. As voltage is applied to the gate electrode having such ashape, the shoulder of the active region undergoes an electric fieldconcentration so that a transistor having a lower threshold voltage isformed. This parasitic transistor forms the hump characteristicsindicated by the curve h shown in FIG. 9H.

[0025] As seen from the curve h, the drain current at a higher gatevoltage is lower than that of the curve r. As heat treatment isperformed in order to make dense the silicon oxide buried in the trench,the silicon oxide layer 9 contracts so that the active region surroundedby the silicon oxide film 9 receives a compression stress.

[0026] As the compression stress is applied, the mobility ofelectron/hole in the active region of the silicon substrate 1 may lower,which reduces the saturated drain current. As the element is made finerand the area of the active region is made small, the influence of thecompression stress increases.

[0027] In IEDM 1988, pp. 92-95, B. Davari et al. have proposed toimplant ions into the shoulder of an active region in order to suppressthe hump characteristics.

[0028] Another method has been proposed to round the shoulder of anactive region through thermal oxidation in order to suppress the humpcharacteristics. Since the shoulder is rounded and the electric fieldconcentration is relaxed, the influence of a parasitic transistor can bemitigated.

[0029] In IEDM 1992, pp. 57-60, Pierre C. Fazan et al. have proposed toform insulating side wall spacers on the side walls of an isolationsilicon oxide film protruding from an upper surface of a siliconsubstrate to thereby bury divots.

[0030] Although STI is suitable for the microfine structure ofsemiconductor devices, there occur problems specific to STI. Newtechniques capable of solving the problems specific to STI have beendesired to date.

SUMMARY OF THE INVENTION

[0031] It is an object of this invention to provide a semiconductordevice with STI capable of presenting good transistor characteristics.It is another object of the invention to provide a method ofmanufacturing a semiconductor device having good transistorcharacteristics.

[0032] According to one aspect of the present invention, there isprovided a semiconductor device comprising: a silicon substrate withsemiconductor elements; an isolation trench formed in the siliconsubstrate for separating active regions in the silicon substrate, theisolation trench having a trapezoidal cross sectional shape having awidth gradually narrowing with a depth from a surface of the siliconsubstrate; a first liner insulating film formed on a surface of thetrench and made of a silicon oxide film or a silicon oxynitride filmhaving a thickness of 1 to 5 nm; a second liner insulating film formedon the first liner insulating film and made of a silicon nitride filmhaving a thickness of 2 to 8 nm; and an isolation region burying thetrench defined by the second liner insulating film.

[0033] According to another aspect of the present invention, there isprovided a method of manufacturing a semiconductor device, comprisingsteps of: (a) forming a polishing stopper layer on a surface of asilicon substrate, the stopper layer including a silicon oxide film anda silicon nitride film; (b) etching the stopper layer and the siliconsubstrate by using a mask to form a trench; (c) forming a first linerinsulating film on a surface of the silicon substrate exposed in thetrench, the first liner insulating film being a silicon oxide film or asilicon oxynitride film having a thickness of 1 to 5 nm; (d) forming asecond liner insulating film on the first liner insulating film, thesecond liner insulating film being made of a silicon nitride film havinga thickness of 2 to 8 nm; (e)-depositing an isolation layer on thesilicon substrate, the isolation layer burying the trench defined by thesecond liner insulating film; (f) polishing and removing an unnecessaryportion of the isolation layer by using the stopper layer as a polishingstopper; and (g) etching the stopper layer.

[0034] As above, it is possible to provide a transistor device with STIand relaxed electric field concentration on the shoulders of an activeregion, and its manufacture method.

[0035] Since a silicon nitride film is left at least on the side wallsof a trench, a tensile stress is applied to the channel region of theactive region so that a reduction in the mobility can be relaxed.

[0036] The formation of a hump and the reverse narrow channel effectscan be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037]FIGS. 1A to 1H are cross sectional views illustrating a method ofmanufacturing a semiconductor device according to an embodiment of theinvention.

[0038]FIGS. 2A and 2B are a plan view and a cross sectional view showinga semiconductor device manufactured by the embodiment method illustratedin FIGS. 1A to 1H.

[0039]FIGS. 3A and 3B are graphs showing the characteristics of asemiconductor device manufactured by the embodiment method illustratedin FIGS. 1A to 1H, as compared to the characteristics of a semiconductordevice of prior art.

[0040]FIGS. 4A and 4B are a graph showing the effects of a siliconnitride film left on the side walls of a trench and a graph showing thedependency of a saturated drain current upon a source/drain width.

[0041]FIGS. 5A to 5D are cross sectional views illustrating a method ofmanufacturing a semiconductor device according to another embodiment ofthe invention.

[0042]FIGS. 6A to 6D are cross sectional views illustrating a method ofmanufacturing a semiconductor device according to a further embodimentof the invention.

[0043]FIGS. 7A to 7H are cross sectional views illustrating a method ofmanufacturing a semiconductor device according to still anotherembodiment of the invention.

[0044]FIGS. 8A to 8K are cross sectional views illustrating a method ofmanufacturing a semiconductor device according to still anotherembodiment of the invention.

[0045]FIGS. 9A to 9H are cross sectional views illustrating a method ofmanufacturing a semiconductor device according to prior art and a graphshowing the characteristics of a transistor manufactured by this method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Embodiments of the invention will be described with reference tothe accompanying drawings.

[0047]FIGS. 1A to 1H are schematic cross sectional views illustratingmain processes of a method of manufacturing a semiconductor deviceaccording to an embodiment of the invention.

[0048] As shown in FIG. 1A, the surface of a silicon substrate 1 isthermally oxidized to form a silicon oxide film 2 having a thickness of9 to 21 nm, e.g., 10 nm. On the silicon oxide film 2, a silicon nitridefilm 3 having a thickness of 100 to 150 nm is formed by low pressure(LP) chemical vapor deposition (CVD). For example, LPCVD is performed ata temperature of 700° C. by using SiCl₂H₂ and NH₃ as source gas.

[0049] A resist film is coated on the silicon nitride film 3, exposedand developed to form a resist pattern 4. The resist pattern 4 has anopening or openings for defining an isolation region or regions andactive regions (element regions) each surrounded by the isolationregion. The width of an opening 5 a is, for example, 0.2 to 1 μm.

[0050] By using the resist pattern 4 as an etching mask, the siliconnitride film 3, silicon oxide film 2 and silicon substrate 1 are etched.The silicon substrate 1 is etched by a depth of 0.5 μm to form a trench6. For example, the silicon nitride film and silicon oxide film areetched by using mixture gas of CF₄+CHF₃+Ar as etchant, and the siliconsubstrate 1 is etched by using mixture gas of HBr+O₂ or Cl₂+O₂ asetchant.

[0051] With these etching conditions, the side walls of the trench 6have slanted surfaces. With these slanted surfaces, electric fieldconcentration upon the shoulder of the active region can be relaxed. Theresist pattern 4 is thereafter removed.

[0052] As shown in FIG. 1B, the silicon substrate surface exposed in thetrench 6 is thermally oxidized to form a silicon oxide film 7 having athickness of 1 to 5 nm. The whole silicon surface exposed in the trench6 is covered with the silicon oxide film 7.

[0053] As shown in FIG. 1C, a silicon nitride film 8 is formed by LPCVD,covering the surfaces of the silicon oxide film 7 and silicon nitridefilm 3. The thickness of the silicon nitride film 8 is 2 to 8 nm. Thisthickness of 2 to 8 nm of the silicon nitride film 8 makes it difficultfor hot phosphoric acid to be used for etching silicon nitride topenetrate into this thin film 8.

[0054] LPCVD is performed at a temperature of about 650° C. by usingmixture gas of SiCl₂H₂+NH₃ as source gas. The silicon nitride filmformed by such thermal CVD has a tensile stress of 1 GPa or larger. Thedirection of this stress is opposite to that of the stress in a buriedsilicon layer after heat treatment for making it dense to be describedlater. The thickness of 1 to 5 nm of the silicon oxide film 7 makes itdifficult for dilute hydrofluoric acid to be used for etching siliconoxide to penetrate into this thin film 7.

[0055] As shown in FIG. 1D, a silicon oxide layer 9 is deposited overthe substrate with the silicon nitride film 8, for example, by highdensity plasma (HDP) CVD, the silicon oxide layer 9 burying the trench.If the trench has a depth of 0.5 μm, the thickness of the silicon layer9 is set to about 0.6 to 1 μm in the flat area.

[0056] The silicon oxide layer is formed by using mixture gas of SiH₄and oxygen or TEOS and ozone as source gas. After the silicon oxidelayer 9 is grown, annealing at about 1000° C. is performed to make thesilicon oxide layer 9 dense. The film quality of the silicon oxide layer9 in the trench after the annealing is approximately similar to that ofthe thermally oxidized film. Although the dense silicon oxide layer hasa compression stress, the directions of this compression stress and thetensile stress of the silicon nitride film are opposite so that both thestresses are cancelled out. The mobility can therefore be prevented frombeing lowered by the compression stress.

[0057] As shown in FIG. 1E, an unnecessary region of the silicon oxidelayer 9 at a position higher than the silicon nitride films 3 and 8 isremoved by performing chemical mechanical polishing (CMP). CMP isperformed by holding the silicon substrate between upper and lowerrotating surface plates which are controlled to have, for example, arevolution speed of 20 rpm, a pressure of 5 psi therebetween and a backpressure of 5 psi. As polishing agent, slurry mainly containingcolloidal silica or cerium oxide slurry is used.

[0058] Under such polishing conditions, an etching rate of the siliconnitride film 3 is small so that the silicon nitride film 3 functions asa polishing stopper. In the state after the polishing, the silicon oxidelayer 9 is approximately flush with the silicon nitride film 3, and thesilicon oxide layer 9 is left only in the opening defined by the siliconnitride film 3. In this example, although the silicon oxide layer 9 at aposition higher than the silicon nitride film 3 is removed by CMP, itmay be removed by RIE using mixture gas of CF₄+CHF₃.

[0059] As shown in FIG. 1F, the silicon nitride film 3 is etched by hotphosphoric acid. At this time, the silicon nitride film 8 on the sidewall of the silicon nitride film 3 is also etched. As the siliconnitride film 3 is removed, the upper surface of the silicon nitride film8 between the silicon oxide film 7 on the silicon substrate 1 and theburied silicon oxide layer 9 is exposed.

[0060] Since the thickness of the silicon nitride film 8 is set as thinas 2 to 8 nm, hot phosphoric acid having a relatively high viscosity ishard to penetrate into this thin film so that the silicon nitride film 8between the silicon oxide film 7 and silicon oxide layer 9 is hardlyetched.

[0061] As the silicon nitride film 3 and the silicon nitride film 8 onthe side wall of the silicon nitride film 3 are removed by hotphosphoric acid, the upper portion of the silicon oxide layer 9protrudes from the surface of the silicon substrate 1 as shown in FIG.1F.

[0062] Thereafter, the silicon oxide film 2 on the surface of thesilicon substrate 1 is removed by dilute hydrofluoric acid. At thistime, the protruded silicon oxide layer 9 is also etched slightly.

[0063] The upper surface of the silicon oxide film 7 formed on thetrench surface is also exposed. Since the thickness of the silicon oxidefilm 7 is set as thin as 1 to 5 nm, dilute hydrofluoric acid is hard toenter this thin film so that the silicon oxide film 7 is hardly etched.

[0064] As shown in FIG. 1G, the surface of the silicon substrate 1 isthermally oxidized to grow a sacrificial oxide film 22.

[0065] By using the sacrificial oxide film 22 as a through oxide film,ions are implanted into the surface layer of the silicon substrate 1.Implanted impurity ions are activated to form wells 10 having apredetermined conductivity type. For example, n- and p-type wells areformed independently by ion implantation using resist masks. After thewell 10 is formed, the sacrificial oxide film is removed by dilutehydrofluoric acid.

[0066] A plurality of hydrofluoric acid etching processes etch theprojected portion of the silicon oxide layer 9 and divots are formedalong the side of the shoulder of the active region. However, thesilicon nitride film 8 and silicon oxide film 7 are hardly etched andthey cover the side of the active region.

[0067] If buffered hydrofluoric acid mixed with NH₄H having a viscosityhigher than dilute hydrofluoric acid is used, it is possible to suppressetching the silicon oxide film 7 more reliably.

[0068] As shown in FIG. 1H, the sacrificial oxide film is removed andthe exposed surface of the silicon substrate 1 is thermally oxidized toform a gate insulating oxide film 11 having a thickness of, e.g., 2 nm.Prior to forming the gate insulating oxide film 11, dilute hydrofluoricacid etching is performed to such an extent that a thermally oxidizedfilm would be etched by 20 nm. A polysilicon layer 12 is formed over thesubstrate surface and patterned to form a gate electrode. Thereafter,impurity ions of a conductivity type opposite to that of the well 10 areimplanted to form source/drain regions on both sides of the gateelectrode. If necessary, side wall spacers are formed on the side wallsof the gate electrode, and impurity ions are implanted and activated toform high impurity concentration source/drain regions.

[0069]FIG. 2A is a plan view showing the layout of active regions ARdefined by an isolation region 9 and a gate electrode 12 formed on thesurface of a silicon substrate. FIGS. 1A to 1H are the cross sectionalviews taken along line B-B′ in FIG. 2A. Each active region AR issurrounded by the isolation region 9. A MOS inverter is constituted oftwo active regions.

[0070] The plan view of FIG. 2A shows the state before side wall spacersare formed. After the side wall spacers are formed, impurity ions havinga conductivity type opposite to that of the wells are implanted to formhigh impurity concentration source/drain regions.

[0071]FIG. 2B is a cross sectional view taken along a line A-A′ shown inFIG. 2A. As shown in FIG. 2B, the side wall spacers SW are formed on theside walls of the gate electrode, and the source/drain regions S/D areformed on both sides of the gate electrode. A silicide film 13 is formedon the upper surfaces of the gate electrode 12 and source/drain regionsS/D. A silicon oxide film 7 and a silicon nitride film 8 are made verythin so that etchant cannot enter these films and upper surfaces thereofare left scarcely etched.

[0072] Since the upper surface of the silicon nitride film 8 ispositioned not lower than the surface of the silicon substrate, thetensile stress of the silicon nitride film 8 is applied effectively tothe channel region.

[0073]FIG. 3A shows the characteristics of a n-type MOS transistorformed by the processes described previously. The characteristics of theMOS transistor having a gate length of 0.1 μm and a gate width of 1 μmwere measured. A curve p shows the characteristics of a transistor ofconventional techniques, and a curve s shows the characteristics of atransistor of an embodiment. It was confirmed that a saturated draincurrent increased and the mobility to be otherwise lowered by acompression stress was maintained by the tensile stress of the nitridefilm. The saturated drain current was improved by 5%. The existence of aparasitic MOS transistor was not confirmed and the absence of a hump wasconfirmed. The reverse narrow channel effect was also studied.

[0074]FIG. 3B is a graph showing the measurement results. A curve pshows the characteristics of a transistor of conventional techniques,and a curve s shows the characteristics of a transistor of anembodiment. According to the conventional techniques, as the gate widthis made narrow, the threshold voltage gradually lowers, which indicatesthe existence of the reverse short channel effect. In contrast, it canbe seen from the curve s of the embodiment that even if the gate widthis made narrow, the threshold voltage scarcely lowers and that thereverse narrow channel effect can be suppressed. This may be ascribed tothat there is less contribution of a parasitic MOS transistor.

[0075] A tensile stress in a channel region relative to an indent-ordepression amount of an upper surface of a liner silicon nitride filmformed on the inner surface of a trench was simulated by changing theindent position of the upper surface of the silicon nitride film fromthe surface of the semiconductor substrate.

[0076]FIG. 4A is a graph showing how the tensile stress in the channelregion of an active region changes with the depression amount of a sidewall silicon nitride film from a silicon substrate surface. Thedepression amount is 0 when the surface of the silicon nitride film isflush with the surface of the semiconductor substrate, and it increasesas the silicon nitride film is depressed from the semiconductorsubstrate surface. The tensile stress in the channel region reduces asthe depression amount of the silicon nitride film increases. If thesilicon nitride film is depressed by about 30 nm or more, it can beconsidered that the effects of the silicon nitride film disappearnearly.

[0077] In other words, the tensile stress can be effectively applied tothe channel region in the active region by limiting the depressionamount of the silicon nitride film from the surface of the semiconductorsubstrate. The tensile stress can be applied effectively to the channelregion by setting the depression amount to about 10 nm or smaller.

[0078] A change in the saturated drain current relative to the width (SDwidth) of a source/drain region along the source/drain direction wasalso measured.

[0079]FIG. 4B is a graph showing a change in the saturated drain currentrelative to the SD width. According to conventional techniques, as theSD width becomes narrow, the saturated drain current Ids lowers.According to the embodiment, even if the SD width becomes narrow, thesaturated drain current Ids is maintained almost constant.

[0080] In this embodiment, the liner silicon nitride film is formed fromthe bottom surface to side wall of the trench. The liner silicon nitridefilm 5 may be formed extending to the upper surface of the activeregion.

[0081]FIGS. 5A to 5D are cross sectional views illustrating mainprocesses of a method of manufacturing a semiconductor device accordingto another embodiment of the invention.

[0082] After processes similar to those described with reference to FIG.1A are performed, a silicon nitride film 3, a silicon oxide film 2 and asemiconductor substrate 1 are etched by using a resist pattern as anetching mask to form a trench 6 in the semiconductor substrate.

[0083] As shown in FIG. 5A, the silicon oxide film 2 is side-etched bydilute hydrofluoric acid solution to retract the silicon oxide film 2 byabout 10 nm from the side walls of the silicon nitride film 3. Theresist pattern is removed either before or after this side etching.

[0084] As shown in FIG. 5B, similar to the above-described embodiment,the substrate surface exposed in the trench and in the retracted spaceof the silicon oxide film 2 is thermally oxidized to form a siliconoxide film 7 having a thickness of 1 to 5 nm. Thereafter, similar to theprocess in FIG. 1C, a silicon nitride film 8 having a thickness of 2 to8 nm is formed over the whole surface of the substrate by CVD.

[0085] The thickness of the silicon oxide film 2 is set to such a valuethat the retracted space of the silicon oxide film 2 is not completelyfilled with the silicon nitride film 8. For example, assuming that thethickness of the silicon oxide film 2 is 15 nm, a twofold of a totalthickness of the silicon oxide film 7 and silicon nitride film 8 is setthinner than 15 nm.

[0086] As shown in FIG. 5B, a silicon oxide layer 9 is deposited, forexample, by HDP-CVD, the trench being buried with the silicon oxidelayer 9. Thereafter, similar to the process in FIG. 1F, an unnecessaryportion of the silicon oxide layer 9 at the position higher than thesilicon nitride films 3 and 8 is removed by CMP. Annealing is performedin order to make the silicon oxide layer 9 dense.

[0087] As shown in FIG. 5C, the silicon nitride film 3 and the siliconnitride film 8 in contact with the former film 8 are etched by hotphosphoric acid. In this case, a portion of the silicon nitride film 8between the silicon oxide film 2 and silicon oxide layer 9 is hardlyetched because the thickness of the silicon nitride film 8 is as thin as2 to 8 nm. As a result, a lamination of the silicon oxide film 7 andsilicon nitride film 8 is left on the shoulder of the active region ofthe silicon substrate 1. Thereafter, similar to the previously describedembodiment, the silicon oxide film 2 is removed and a sacrificial oxidefilm is grown to thereafter perform ion implantation and activation.

[0088] As shown in FIG. 5D, after the sacrificial film is removed and agate oxide film 11 is formed, a polysilicon layer 12 is deposited andpatterned to form a gate electrode.

[0089] In this embodiment, the lamination layer of the silicon oxidefilm 7 and silicon nitride film 8 is left on the shoulder of the activeregion. Therefore, the tensile stress applied to the channel regionbecomes large as shown in FIG. 4A. The polysilicon gate electrode 12formed on the lamination layer faces the shoulder of the active regionvia the insulating lamination layer thicker than the gate insulatingfilm. Therefore, the electric field concentration can be relaxed.

[0090] A method of leaving the lamination layer of the silicon oxidefilm and silicon nitride film on the shoulder of the active region isnot limited to the above embodiment.

[0091]FIGS. 6A to 6D are cross sectional views illustrating mainprocesses of a method of manufacturing a semiconductor device accordingto a further embodiment of the invention.

[0092] As shown in FIG. 6A, after a trench is etched, the trench surfacein the semiconductor substrate 1 is thermally oxidized to form a siliconoxide film 7 having a thickness of 1 to 5 nm. Next, the silicon nitridefilm 3 is etched, for example, by about 10 nm by hot phosphoric acid.Since the silicon oxide films 2 and 7 are not etched, only the siliconnitride film 3 is etched so that the silicon nitride film 3 isretracted, for example, by about 10 nm from the side walls of thesilicon oxide layer 7. After the side walls of the silicon nitride film3 are retracted, a silicon nitride film 8 having a thickness of 2 to 8nm is formed.

[0093] As shown in FIG. 6B, a silicon oxide layer 9 is deposited on thesurface of the semiconductor substrate, for example, by HDP-CVD, thetrench being buried with the silicon oxide layer 9. The shoulder of theactive region of the substrate 1 is covered with portions of the siliconoxide films 2 and 7 and silicon nitride film 8 on which the siliconoxide layer 9 is deposited.

[0094] CMP is then performed to remove an unnecessary portion of thesilicon oxide layer 9 at the position higher than the surface of thesilicon nitride film 3.

[0095] As shown in FIG. 6C, the silicon nitride film 3 and the siliconnitride film 8 in contact with the former film 3 are etched by hotphosphoric acid. In this case, a portion of the silicon nitride film 8between the silicon oxide films 2 and 7 and silicon oxide layer 9 ishardly etched because the hot phosphoric acid does not penetrate intothe portion of the silicon nitride film.

[0096] Thereafter, similar to the previously described embodiment, thesilicon oxide film 2 is removed and a sacrificial oxide film is grown tothereafter perform ion implantation and activation and then remove thesacrificial oxide film.

[0097] As shown in FIG. 6D, a gate oxide film 11 is formed on theexposed surface of the active region. Although the silicon oxide layer 9has divots etched along the side of the shoulder of the active region,the shoulder is maintained covered with the silicon oxide films 2 and 7and silicon nitride film 8. A polysilicon layer is deposited andpatterned to form a gate electrode. Similar to the embodiment shown inFIGS. 5A to 5D, since the shoulder of the active region is covered withthe lamination layer of the silicon oxide films and silicon nitridefilm, a large tensile stress is applied to the channel region so that anelectric field concentration is relaxed when a voltage is applied to thegate electrode.

[0098] In the embodiments described above, the surface of a trench iscovered with a liner insulating film made of a lamination layer of asilicon oxide film and a silicon nitride film. The liner insulating filmmay be made of a single film.

[0099]FIGS. 7A to 7H are cross sectional views illustrating mainprocesses of a method of manufacturing a semiconductor device accordingto still another embodiment of the invention.

[0100] As shown in FIG. 7A, after a trench is etched, a silicon oxidefilm 2 is side-etched to retract the side walls of the silicon oxidefilm 2 by about 10 nm from the side walls of a silicon nitride film 3.This process is similar to the process in FIG. 5A. The condition oflimiting the thickness of the silicon oxide film 2 is, however,different.

[0101] As shown in FIG. 7B, the shoulder of the active region and thebottom corners of the trench are rounded, for example, by chemical dryetching. This dry etching removes the surface layer of the trench, andthe layer damaged by trench etching, if any, is removed. The shoulder ofthe active region is rounded to a circular cross sectional shape havinga radius of curvature approximately equal to the retraction amount ofthe silicon oxide film 2. The silicon surface after dry etching is aclean surface with fewer defects.

[0102] As shown in FIG. 7C, a silicon nitride film 8 having a thicknessof 2 to 8 nm is formed on the surface of the semiconductor substrate byCVD. If the thickness of the silicon oxide film 2 is set greater than atwofold of the thickness of the silicon nitride film 8, it is possibleto prevent the retracted space from being buried with the siliconnitride film 8. For example, assuming that the thickness of the siliconoxide film 2 is 15 nm, the thickness of the silicon nitride film 8 isset to 5 nm.

[0103] As shown in FIG. 7D, after the silicon nitride film 8 is formed,a silicon oxide layer 9 is deposited to bury the trench.

[0104] As shown in FIG. 7E, the silicon oxide layer 9 is polished by CMPusing the silicon nitride film 9 as a polishing stopper. After thesurface of the silicon oxide film 9 is planarized, annealing isperformed, for example, for 30 minutes at 1000° C. in an N₂ atmospherein order to make the buried silicon oxide film dense.

[0105] As shown in FIG. 7F, the silicon nitride film 3 is etched by hotphosphoric acid. Portions of the silicon nitride film 8 between thesilicon substrate 1 and silicon oxide layer 9 and between the siliconoxide film 2 and silicon oxide layer 9 are left unetched because the hotphosphoric acid cannot penetrate into the portions of the siliconnitride film 8.

[0106] As shown in FIG. 7G, the silicon oxide film 2 is removed, asacrificial film is grown, and ion implantation and activation isperformed. After the sacrificial film is removed, a gate oxide film 11is formed by thermal oxidation. Although the upper portion of thesilicon oxide layer 9 is etched by the dilute hydrofluoric acid processof removing the silicon oxide film, the silicon nitride film 8 coveringthe shoulder of the active region is left unetched.

[0107] As shown in FIG. 7H, a polysilicon layer 12 is deposited coveringthe gate oxide film 11, and patterned to form a gate electrode. Sincethe shoulder of the active region is rounded, the degree of an electricfield concentration can be mitigated when a voltage is applied to thegate electrode.

[0108] In the embodiments described above, a silicon oxide film and asilicon nitride film are formed on the surface of a silicon substrate,and the silicon nitride film is used as the CMP stopper. A laminationlayer having a different structure may be formed on a semiconductorsubstrate.

[0109]FIGS. 8A to 8K are cross sectional views illustrating mainprocesses of a method of manufacturing a semiconductor device accordingto still another embodiment of the invention.

[0110] As shown in FIG. 8A, a silicon oxide film 2 similar to those ofthe above-described embodiments is formed on the surface of asemiconductor substrate 1. On this silicon oxide film 2, an amorphoussilicon film 2 a is formed. On this amorphous silicon film 2 a, asilicon nitride film 3 similar to those of the above-describedembodiments is formed. A photoresist layer is coated on the surface ofthe silicon nitride film 3, and exposed and developed to form a resistpattern 4.

[0111] As shown in FIG. 8B, by using the resist pattern 4 as an etchingmask, the silicon nitride film 3, amorphous silicon film 2 a and siliconoxide film 2 are etched and then the silicon substrate is etched to forma trench 6.

[0112] As shown in FIG. 8C, the amorphous silicon film 2 a isselectively etched. For example, isotropic etching in a liquid phase isperformed by using HF+HNO₃+H₂O or HF+NH₄OH+H₂O₂+H₂O to retract the sidewalls of the amorphous silicon film 2 a. During this etching, thesilicon substrate 1 is scarcely etched because of a difference of anetching selection ratio between the amorphous silicon film and crystalsilicon.

[0113] As shown in FIG. 8D, the exposed silicon surface is oxidized. Asilicon oxide film 7 a is formed on the amorphous silicon film 7 and asilicon oxide film 7 is formed on the silicon substrate. Instead ofoxidizing the silicon surface, it may by oxynitridized. The thickness ofthe silicon oxide film or silicon oxynitride film is set to such a valuethat etchant for etching silicon oxide in a later process is hard topenetrate into the film. The silicon oxynitride film has a smalleretching rate than the silicon oxide film so that the detraction amountby etching can be reduced.

[0114] As shown in FIG. 8E, a silicon nitride film 8 is formed on thewhole surface of the substrate to a thickness of, e.g., 5 nm by CVD. Thethickness of the silicon nitride film 8 is set to such as value that hotphosphoric acid etchant does not penetrate into the silicon nitride film8.

[0115] As shown in FIG. 8F, a silicon oxide layer 9 is deposited buryingthe trench. As shown, the shoulder of the active region is covered witha lamination layer of the silicon oxide film 7 and silicon nitride film8, and the silicon oxide layer 9 covers the lamination layer.

[0116] As shown in FIG. 8G, CMP is performed to remove an unnecessaryportion of the silicon oxide layer 9 at the position higher than thesilicon nitride film 3. The state shown in FIG. 8G shows the siliconnitride film 3 partially removed. CMP is performed to the extent thatthe silicon nitride film 3 appears and is not removed completely.

[0117] As shown in FIG. 8H, the silicon nitride film is removed by hotphosphoric acid. With this etching, the exposed silicon nitride film 3and the silicon nitride film 8 in contact with the former film areetched. However, since the thickness of the silicon nitride film 8 isselected to such an extent that the hot phosphoric acid does notpenetrate into the silicon nitride film 8, the retraction amount of thesilicon nitride film 8 from the upper surface thereof is limited.

[0118] As shown in FIG. 8I, the amorphous silicon film 2 a is removed byNH₃+H₂O+isopropyl alcohol (IPA).

[0119] As shown in FIG. 8J, the silicon oxide films 2 and 7 a areremoved. This etching slightly etches the surface of the silicon oxidelayer 9. The nitride film 8, when projected, may be removed since it isvery thin. Thereafter, a sacrificial film is formed and ion implantationand activation is performed to form wells 10. After the sacrificial filmis removed, a gate oxide film is formed on the exposed surface of theactive region.

[0120] As shown in FIG. 8K, a polysilicon film is formed covering thegate insulating film 11, and patterned to form a gate electrode 12. Theshoulder of the active region is maintained covered with the siliconoxide film 7 and silicon nitride film 8. Depending upon the processconditions, a portion of the silicon oxide layer 9 is left on thesilicon nitride film 8. Since the gate electrode 12 is formed on thisstructure, an electric field concentration upon the shoulder of theactive region can be relaxed when a voltage is applied to the gateelectrode. A large tensile stress is applied to the channel region.

[0121] The present invention has been described in connection with thepreferred embodiments. The invention is not limited only to the aboveembodiments. It is apparent that various modifications, improvements,combinations, and the like can be made by those skilled in the art.

What we claim are:
 1. A semiconductor device comprising: a siliconsubstrate with semiconductor elements; an isolation trench formed insaid silicon substrate for isolating active regions in said siliconsubstrate, said isolation trench having a trapezoidal cross sectionalshape having a width gradually narrowing with a depth from a surface ofsaid silicon substrate; a first liner insulating film formed on asurface of said trench and made of a silicon oxide film or a siliconoxynitride film having a thickness of 1 to 5 nm; a second linerinsulating film formed on said first liner insulating film and made of asilicon nitride film having a thickness of 2 to 8 nm; and an isolationregion burying said trench defined by said second liner insulating film.2. A semiconductor device according to claim 1, wherein an upper end ofsaid second liner insulating film is retracted by less than about 10 nmfrom the surface of said silicon substrate.
 3. A semiconductor deviceaccording to claim 1, wherein said first and second liner insulatingfilms extend from side walls of said trench to an upper surface of thesilicon substrate.
 4. A semiconductor device according to claim 3,wherein said isolation region includes a portion extending on saidsecond liner insulating layer above the upper surface of said siliconsubstrate.
 5. A semiconductor device according to claim 4, wherein saidsecond liner insulating film includes a portion extending on side wallsof said extending portion of said isolation region.
 6. A semiconductordevice according to claim 1, wherein said second liner insulating filmhas a tensile stress of 1 GPa or larger.
 7. A semiconductor devicecomprising: a silicon substrate with semiconductor elements; anisolation trench formed in said silicon substrate for isolating activeregions in said silicon substrate, said isolation trench havinggenerally a trapezoidal cross sectional shape having a width graduallynarrowing with a depth from a surface of said silicon substrate andhaving a gradually broadening upper portion, said isolation trenchdefining the active regions with rounded shoulders; a liner insulatingfilm formed on a surface of said trench and made of a silicon nitridefilm having a thickness of 2 to 8 nm; and an isolation region buryingsaid trench defined by said liner insulating film.
 8. A semiconductordevice according to claim 7, wherein a cross sectional shape of theshoulder of the active region is approximately a segment of a circle. 9.A semiconductor device according to claim 7, wherein said linerinsulating film applies a tensile stress of 1 GPa or larger to theactive region.
 10. A semiconductor device according claim 7, furthercomprising an underlying liner layer of silicon oxide between thesurface of said trench and said line insulating film.
 11. A method ofmanufacturing a semiconductor device, comprising steps of: (a) forming apolishing stopper layer on a surface of a silicon substrate, saidstopper layer including a lower silicon oxide film and an upper siliconnitride film; (b) etching said stopper layer and the silicon substrateby using a mask to form a trench; (c) forming a first liner insulatingfilm on a surface of the silicon substrate exposed in said trench, saidfirst liner insulating film being a silicon oxide film or a siliconoxynitride film having a thickness of 1 to 5 nm; (d) forming a secondliner insulating film on said first liner insulating film, said secondliner insulating film being made of a silicon nitride film having athickness of 2 to 8 nm; (e) depositing an isolation layer on saidsilicon substrate, said isolation layer burying said trench defined bysaid second liner insulating film; (f) polishing and removing anunnecessary portion of said isolation layer by using said stopper layeras a polishing stopper; and (g) etching said stopper layer.
 12. A methodaccording to claim 11, further comprising between said steps (b) and (c)a step of: (h) side-etching the silicon oxide film of said stopper layerto form retracted portions of the silicon oxide film.
 13. A methodaccording to claim 12, wherein thicknesses of the silicon oxide film ofsaid stopper layer and said first and second liner insulating films areset to such values that said retracted portions are not buried by thefirst and second liner insulating films.
 14. A method according to claim11, further comprising between said steps (b) and (c) a step of: (i)etching the silicon nitride film of said stopper layer to form retractedportions of the silicon nitride film and partially expose partial uppersurfaces of the underlying silicon oxide film.
 15. A method according toclaim 11, wherein said stopper layer includes, from lower position, asilicon oxide film, an amorphous silicon film and a silicon nitride filmand the method further comprises between said steps (b) and (c) a stepof: (j) side-etching the amorphous silicon film to form retractedportions of the amorphous silicon film.
 16. A method according to claim11, wherein said step (d) forms a silicon nitride film having a tensilestress of 1 GPa or larger.
 17. A method according to claim 11, whereinsaid step (g) includes a step of etching the silicon nitride film ofsaid stopper layer by hot phosphoric acid.
 18. A method according toclaim 11, wherein said step (g) includes a step of etching the siliconoxide film of said stopper layer by dilute hydrofluoric acid or bufferedhydrofluoric acid.
 19. A method of manufacturing a semiconductor device,comprising steps of: (a) forming a polishing stopper layer on a surfaceof a silicon substrate, said stopper layer including a lower siliconoxide film and an upper silicon nitride film; (b) etching said stopperlayer and the silicon substrate by using a mask to form a trench in anisolation region defining active regions; (c) side-etching the siliconoxide film of said stopper layer to retract side walls of the siliconoxide film; (d) etching silicon to round a shoulder of the active regionexposed by the retracted side wall; (e) forming a liner insulating filmon the surface of the silicon substrate, said liner insulating filmbeing made of a silicon nitride film having a thickness of 2 to 8 nm;(f) depositing an isolation layer on said silicon substrate, saidisolation layer burying said trench defined by said liner insulatingfilm; (g) polishing and removing an unnecessary portion of saidisolation layer by using said stopper layer as a polishing stopper; and(h) etching said stopper layer.
 20. A method according to claim 19,wherein said step (e) forms a silicon nitride film having a tensilestress of 1 GPa or larger.
 21. A method according to claim 19, whereinsaid step (h) includes a step of etching the silicon nitride film by hotphosphoric acid.